1. Field of the Invention
This invention relates generally to configurable gate arrays and, more particularly, to a configurable gate array having an on chip test system.
2. Background Art
Configurable gate arrays traditionally operate in either an asynchronous mode or a synchronous (pipeline) mode. In the asynchronous mode, signals are applied directly through the input pins to the gates of the array. In the pipeline mode, shift registers are coupled between each of the input pins and the gates of the array for clocking each of the signals from the input pins to the gates of the array simultaneously.
Gate arrays, and large scale integrated (LSI) circuits in general, have become so complex, that initial testing and subsequent maintenance of these circuits have become a major challenge. Earlier conventional methods applied test vectors through input pins and compared the output of the chip with an expected output. However, this method is time consuming, expensive, and presents a difficult task of determining a set of test vectors that is both valid and complete. Furthermore, connection of electrical test equipment to the chip in a test environment does not provide error free and repeatable performance. Thus, the testing of arrays requiring mechanical connection of the test equipment to the chip is not desirable.
One more recent known method comprises an on chip test system having internal storage elements designed so that they may operate as shift registers for self testing and diagnostic functions. Sequential logic elements are provided so that test and diagnostic operations are not dependent upon signal transition times or transmission delays, thus allowing for the transformation of sequential logic to combinational logic for testing. However, independent shift registers are not provided for the self test functions.
Another known method that provides for the maintenance function comprises an enhanced "Set-Scan Loop" known as the Maintenance Node Network. This method connects all internal chip registers into a single-bit stream. Each chip, or node, is able to communicate with one node up-stream and two nodes down-stream. Thus, all chips on a board, or in a system, form a binary tree and are able to receive test vectors from, and send test results back to, a maintenance processor. The registers on a chip exist at the input/output as well as internal to the logic. The Maintenance node network then, is a finite-state machine which operates synchronously with the chip clock.
U.S. Pat. No. 4,357,703 describes a test system for testing of LSI chips at full system clock rates that is resident on the chip under test. The system includes switchable transmission gates to alter logic paths, a control shift register in the test function, an input shift register, an associated test generator and accumulator, an output shift register and an associated generator and accumulator. Test vectors are produced using a shift register connected to all inputs of the logic function under test. Checksum logic, together with a shift register, produce a running checksum of all output states of the module under test at the operative clock rate of the chip.
However, none of the above methods disclose an on chip test system that includes self test and maintenance operation while allowing for both synchronous and pipeline modes of normal operation.
Thus, an on chip system for configurable gate arrays is needed that includes self test and maintenance modes while allowing for both synchronous and pipeline modes of normal operation.